Conference Highlights

20 years of excellence

For more than twenty years, IEEE SOC Conference has been providing a premier forum for the ASIC and SoC community for sharing the latest advances in technologies and applications in that area. Founded in 1987 by the IEEE chapter of Rochester, NY, as a local ASIC Seminar, the conference rapidly grew into a well respected international ASIC conference. As ASICs grew in complexity over the years, the IEEE ASIC Conference was one of the first conferences to pick up the trend towards System-on-Chip integration - back in 1999. Since then, the conference - now renamed to IEEE ASIC/SOC and later to IEEE SOCC - has emerged as the premier technical conference focusing specifically on the field of SoC development and related areas.

In 2007, the conference was held outside of the USA for the very first time, successfully celebrating its 20th anniversary in Hsinchu, Taiwan.

For SOCC 2008 we are back in the USA, in the wonderful city of Newport Beach, CA, close to academic institutions such as UC Irvine, to high-tech companies, and to world-famous theme parks and attractions such as Disneyland, Disney's California Adventure, Downtown Disney, Orange County Zoo, Santa Ana Zoo, Knott’s Berry Farm, world-class golfing, beautiful Southern California beaches, fine shopping, museums, and popular dinner shows.
The conference venue is conveniently located only 1/2 mile from John Wayne Airport, providing special room rates and free airport shuttle service.

The Conference

In its tradition of continuing quality, SOCC 2008 will offer three days of technical papers and one day of tutorials. Please watch this site for updates on distinguished speakers and the technical program. While we are finalizing the program for 2008, you may as well want to take a look at our previous conferences.

Distinguished Speakers

SOCC has a long tradition of inviting high-ranking invited Speakers from Industry and Academia to give Keynote, Plenary, and Luncheon talks.

SOCC 2008 -  Newport Beach, CA

Keynote:

Nick Ilyadis

VP and CTO of Enterprise Networking Group, Broadcom
SOC Challenges in the Terabit Networks Era”

Plenary:

Alexander D. Peleg

Vice President, Mobility Group
Director, Intel Architecture Strategic and Platform Planning
Intel Corporation
Future Trends in PC Computing and their Implications to SoC”

Plenary:

Kamran Eshraghian

President, Eshraghian Laboratories Pty Ltd., and
Ferrero Family Chair in Electrical Engineering,
University of California, Merced.
“Surfing the iSoC Multitechnology Platform: Volumetric Growth beyond Moore's Law”

Luncheon:

David F. Doody

Flight Operations Lead, Cassini Mission Support & Services, NASA Jet Propulsion Lab
“Cassini-Huygens at Saturn”

“Hot Topic”
Plenary:

Iain Richardson

Director, Centre for Video Communications,
The Robert Gordon University, UK
“Dynamic Configuration: Beyond Video Coding Standards”

 A list of our speakers from 1990-2007 can be found here.

Panel Discussion:

Like every year, SOCC 2008 will feature a panel discussion on a hot controversial topic in the SoC area.

Best Paper Award
SPONSORED BY

The authors of the best technical paper will receive a Best Paper Award sponsored by Texas Instruments Inc.

Corporate Sponsors and Exhibitors:

Corporate sponsors of our conference may be present with tabletop displays. For more information on corporate sponsorship, please see our Sponsors page

Guided Tour at NASA JPL:

We are pleased to be able to offer a guided tour at NASA Jet Propulsion Lab in Pasadena. The tour will leave at the hotel on Sep. 16, 2008, 11:30 a.m. Bus transportation and box lunch are included in the tour fee of $25 (see registration form). After arriving at JPL, starting at 1 p.m. you will receive a guided tour of JPL lasting 2-2.5 hours in duration, including a multi-media presentation  entitled "Spirit of Exploration ," which provides an overview of the Laboratory's activities and accomplishments. Guests may also visit the von Karman Visitor Center, the Space Flight Operations Facility, and the In-Situ Instruments Laboratory.

All adults must bring proper government issued photo ID's (for US citizens that means DL, State ID, Military ID or passport; for foreign nationals you will need either a Greencard or passport).
We suggest everyone wear comfortable shoes as there is a lot of walking on the tour, dress appropriate for the weather. Cameras and video recorders are allowed so feel free to bring them.
We will be back at the hotel around 5:00 p.m.

Please note that you have to register for the tour with your full name and citizenship by 8/15.
We have to send a list of all participants to JPL one month ahead of the tour and people not on the list will not be admitted. There will be no late or on-site registration available for the tour.

Tutorial Workshops:

Like at our previous conferences, there will be several embedded tutorials during the technical program, and a full day of tutorial workshops on Saturday. For tutorial proposals, please contact the Tutorial Chair.

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Keynote Speaker

Nick Ilyadis
VP and CTO of Enterprise Networking Group,
Broadcom Corporation
SOC Challenges in the Terabit Networks Era”

Nick Ilyadis is Vice President and CTO of Broadcom’s Enterprise Networking Group.
He is responsible for the product strategy and cross portfolio initiatives for a broad portfolio of chip products that include technologies in Network Switching, Ethernet Controllers, Enterprise WLAN, SerDes, PHY, Processors and Security.
Prior to Broadcom, Mr. Ilyadis was Vice President of Engineering for enterprise data products at Nortel Networks. He has also held engineering positions at Digital Equipment Corporation and Itek Optical Systems.
Mr. Ilyadis holds a MSEE from the University of New Hampshire and a BTEE, from the Rochester Institute of Technology.

Abstract: The worldwide appetite for Internet connectivity and bandwidth continues to grow as the delivery of data, voice and video expands to every corner of the globe. This demand, combined with transformations in computing models centered on cloud computing and thin clients, is driving the need for greater bandwidth and low latency in next-generation networks.

Broadband connectivity serves as the ubiquitous mode of network access for an ever expanding number of both consumer and business users and, as such, the aggregate capacity of the underlying network now demands terabit-based infrastructure equipment.  This talk will focus on the significant bandwidth drivers in today’s networks, along with the challenges inherent in creating SoC designs that enable network infrastructure equipment.

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Plenary Speaker

Alexander D. Peleg
Vice President, Mobility Group
Director, Intel Architecture Strategic and Platform Planning
Intel Corporation
Future Trends in PC Computing and their Implications to SoC”

Alex Peleg is vice president, Intel Mobility Group and director of Intel Architecture Strategic and Platform Planning. In this role he is responsible for driving to resolution key strategic issues regarding Intel Architecture directions across product groups (including certain client roadmap and processor design features).

Previously, Peleg was strategic planning director for the Mobility Group as well as director of strategic planning for the Mobile Platforms Group where he was responsible for defining the strategy and roadmap for Intel products used in notebook computers. Peleg was part of the team based in Israel that defined the features that would be combined into what was later known as the Intel® Centrino® Processor Technology platform.

Peleg joined Intel in 1991 as a microprocessor architect at the Israel Design Center in Haifa. He received his bachelor's degree in computer engineering from the Technion, Israel Institute of Technology in 1989 and his master's degree in electrical engineering in 1991 from the same university. Peleg holds more than 50 patents and has earned an Intel Achievement Award.

Abstract: The trends of growing segmentation of PC computing devices, of which many are sleek mobile form factors, the convergence of compute and communications, the need to respond ever more faster to changing market requirements, and growing emphasis on media content and innovative human interfaces, are driving changes to the way traditional high volume mainstream PC CPUs and core logic are architected and designed.

In this talk, the key future trends in traditional PC computing will be explored and their potential implications to how PC architectures may evolve will be explained.

One of the most important implications is the adoption of aspects of SOC design techniques and methodologies to address needs for higher integration, and ability to proliferate quickly to different market segments.

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Kamran Eshraghian
Founder and President
Eshraghian Laboratories Pty Ltd.
Surfing the iSoC Multitechnology Platform: Volumetric Growth beyond Moore's Law”

Kamran Eshraghian is the President of Eshraghian Laboratories and holder of Ferrero Family Chair in Electrical Engineering at University of California, Merced. He obtained his PhD., MEngSc., and BTech., degrees from the University of Adelaide, South Australia and Dr.-Ing e.h. , from the University of Ulm, Germany, for his work in the integration of nanoelectronics with light-wave technology.
In 1979, he joined the Department of Electrical and Electronic Engineering at the University of Adelaide after spending ten years with Philips Research, both in Europe and Australia. In 1994, he was invited to take up the Foundation Chair of Computer, Electronics and Communications Engineering in Western Australia, and became the Head of School of Engineering and Mathematics and Distinguished University Professor and subsequently became the Director of Electron Science Research Institute.  In 2004, he founded Eshraghian Laboratories as part of his vision for horizontal integration of nanochemistry and nanoelectronics with those of bio- and photon-based technologies, thus creating a new design domain for future iSoC research. In 2001 he was the recipient of the German Mercator Visiting Professorship by the German Science Foundation.
He has lectured widely and presented over 200 workshops in large scale integrated and multitechnology systems. In 1987 he was appointed as the Director of the Centre for Gallium Arsenide VLSI Technology at the University of Adelaide. This was Australia's very first Centre to pursue research in the area of very high Speed processing using Gallium Arsenide as the base technology. Here he made some of the original groundwork in computer vision and robotic engineering based upon insect vision.
He has held over 40 patents and co-authored six textbooks. He was the editor of the Silicon Systems Engineering series published by Prentice Hall. Professor Eshraghian, co-founded six High Technology companies, providing intimate link between University research and industry. He also serves as the Chairman of the Board of Directors of four Hi Tech companies.

Abstract: The science fiction of yesterday depicted by such characters as Captain Kirk of the space ship Enterprise has stretched the minds of researchers that no longer scaling of feature size predicted by Gordon Moore is seen to adequately provide the necessary technology direction. While ITRS is driving the search for fabrication solutions inexorably close towards the physical limits, integration and convergence of disparate technologies promise a solution to the severe problems being encountered as process geometries are reduced.

The evolution of SoC and SiP introduce a 3rd dimension that maybe described in terms of a Volumetric Growth Law” that takes into account the multitechnology nature of integration for a future whereby multitechnology integration becomes the new innovation domain. This new frontier of research is conjectured to move us way beyond Gordon Moore's 2-D scaling relationship as we begin to uncover new relationships and principles.

While the future is becoming more difficult to predict, most likely we could anticipate an accelerating pace of change that span health sciences and intelligent health care, environmental management, smart energy management through to new innovations in man-machine interfaces, processing and communications. Embedded biophotonic sensors, for example, that could be powered and monitored remotely to observe a wide range of physiological conditions, such as pulse rate, blood sugar, blood oxygen, blood pressure, status of internal tissues etc., would provide important enabling capabilities. The ability of biomolecules to self-assemble into cells and yield dynamic complexes with highly ordered architectures on nanometer scale provides a further opportunity for cell biology to gain an entry point into manipulation of nano sized circuits. Together with the activities in microfluidic biochips, bio delivery, bio driven actuators, bio photonics, nanoneedles, etc., lead us into Intelligent SoC (iSoC) domain as the new frontier of innovative products. Indications are that in future integration of multitechnologies will be almost impossible both technically and economically unless there is a radical change in thinking towards multitechnology design and processing.

Albert Einstein echoed that “imagination is more important than knowledge” - highly pertinent at this juncture whereby the future of iSoC and iSiP technologies are being mapped.

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Luncheon Speaker

David F. Doody
Flight Operations Lead, Cassini Mission Support & Services,
NASA Jet Propulsion Lab
Cassini-Huygens at Saturn”

Dave Doody came to Pasadena from Catalina Island and started working with JPL's Deep Space Network in 1982, then joined Voyager in the outer solar system three years later. After then serving as a member of the Venus-mapping Magellan flight team, Dave joined Cassini in 1994. He is currently the Flight Operations Lead engineer for Cassini's Mission Support and Services Office. Dave is also an instructor at Art Center College of Design in Pasadena, teaching a Public Programs evening course on the Basics of Interplanetary Flight. And he is working with Praxis-Springer on his book, "Deep Space Craft."
Eager to share the excitement of interplanetary exploration, Dave wrote, and maintains the "Basics of Space Flight" website at JPL (http://www.jpl.nasa.gov/basics). A few times a year you might find him playing "sidewalk astronomer" in Old Town Pasadena, offering free views of Saturn through the JPL Astronomy Club's telescope.

Abstract: The Cassini spacecraft, bristling with telescopes and other scientific instruments, has been orbited Saturn for over 4 years, having completed its prime mission and beginning an extended mission. The European Huygens Probe, that Cassini carried, completed a spectacular descent through Titan's atmosphere. Dave will describe the spacecraft and share some of the stunning discoveries from Saturn and its moons: the planet's unexpected features, a continuous Old Faithful-size geyser on tiny, frozen moon Enceladus, and the rivers and lakes on haze-enshrouded Titan. A report from Cassini wouldn't be complete without also enjoying views from high above Saturn's cloud tops, showing off the magnificent ring system in unprecedented detail. See http://saturn.jpl.nasa.gov for more information

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“Hot Topic” Plenary Speaker

Iain Richardson
Director, Centre for Video Communications,
The Robert Gordon University, UK
“Dynamic Configuration: Beyond Video Coding Standards”

Professor Iain Richardson is the Director of the Centre for Video Communications at the Robert Gordon University, Aberdeen, UK. Prof. Richardson specializes in video compression technology, standards and systems. He wrote the world's first book on the well-known H.264 compression standard, has researched and written extensively on MPEG and H.264 video compression and holds several patents. He provides consulting and analysis services to businesses and industry groups. His current research interests include video codec implementation, human perception and video coding, and dynamic configuration of video codecs.

 

Abstract: Video coding is an enabling technology for an ever-increasing range of applications. Video coding standards such as MPEG-2 and H.264 are considered essential to many of these applications, enabling interoperability between products and systems. However, there are problems associated with standards-based video coding. There is a long timescale between proposing a new video coding technique and its adoption in a standard and subsequent implementation in consumer systems. There is an increasing need for decoders to support multiple, alternative standards. Dynamically adaptive video coding (in which the codec algorithms adapt to suit the video data) can provide significantly improved compression performance but is not supported by fixed, standards-based video codecs.

This talk presents a new approach to video coding, dynamically configurable video compression. In this framework, a universal video decoding engine is dynamically configured as any standard-based or non-standard video decoder, by communicating video decoding functionality and automatically creating the necessary processing structures. This approach has the potential to shorten the time-to-market for new video coding concepts; to reduce the cost of supporting multiple video formats in consumer devices; and to enable significant gains in compression performance through dynamic adaptation. The dynamically configurable coding concept is presented and compared with recent work such as MPEG's Reconfigurable Video Coding standard. Initial results and a first working prototype will be demonstrated.

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