Friday, September 19 - Morning

8:30 a.m. – 10:10 a.m.

FA1:  Reconfigurable Computing 1
Chair: Jürgen Becker, Univ. Karlsruhe, Germany
Co-Chair: Tughrul Arslan, Univ. Edinburgh, UK

FA1.1   Design Space Exploration for Application Specific FPGAs In System-on-a-Chip Designs, Mark Hammerquist and Roman Lysecky, University of Arizona

FA1.2   A Framework of Architectural Synthesis for Dynamically Reconfigurable FPGAs, Ting Liu, Camel Tanougast and Serge Weber, LIEN, Univ. Nancy, France

FA1.3   Reconfigurable Multimedia Accelerator for Mobile Systems, Samar Yazdani1, Joel Cambonie1 and Bernard Pottier2, 1STMicroelectronics and 2Université de Bretagne Occidentale, France

FA1.4   Energy Consumption Reduction Mechanism by Tuning Cache Configuration Using NIOS II Processor, Abel Silva-Filho and Sidney Lima, Universidade de Pernambuco, Brazil

FB1:  Analog and Mixed Signal 2
Chair: Gin-Kou Ma, ITRI
Co-chair: Hongjiang Song, Intel

FB1.1   VLSI Passive Switched Capacitor Signal Processing Circuits: Circuit Architecture, Closed Form Modeling and Applications, Hongjiang Song, Yan Song and Tai-Hua Chen, Intel Corp.

FB1.2   A Novel CMOS Exponential Approximation Circuit, Ming-Lang Lin1, Ahmet Erdogan1, Tughrul Arslan1 and Adrian Stoica2, 1University of Edinburgh, UK, and 2NASA JPL

FB1.3   3-D Heterogeneous SoC for Detecting and Filtering Infected Biological Cells, Vijay Jain, University of South Florida

FB1.4  Novel Mixed Domain VLSI Signal Processing Circuits for High Performance, Low Power and Area Penalty SOC Signal Processing, Hongjiang Song, Intel Corp.

10:10 a.m. - 10:30 a.m.  COFFEE BREAK

10:30 a.m. – 12:10 a.m.

FA2:  Reconfigurable Computing 2
Chair: Tughrul Arslan, Univ. Edinburgh, UK
Co-Chair: Jürgen Becker, Univ. Karlsruhe, Germany

FA2.1    Design of a Baseband Processor for Software Radio Using FPGAs, Ferney Amaya-Fernández1 and Jaime Velasco-Medina2, 1Universidad Javeriana, and 2Universidad del Valle, Colombia

FA2.2    OFDM Symbol Timing Synchronization System on a Reconfigurable Instruction Cell Array, Xin Zhao, Ahmet T. Erdogan and Tughrul Arslan, University of Edinburgh, UK

FA2.3     Reconfigurable Flash A/D Converters, Cristian Onete, NXP Semiconductors, Netherlands

FA2.4     Programmable All-digital Adaptive Deskewing and Phase shifting, Alireza Kaviani, Tao Pi and Declan Kelly, Xilinx Inc

FB2:  Analog and Mixed Signal 3
Chair: Gin-Kou Ma, ITRI
Co-Chair: Hongjiang Song, Intel

FB2.1  A 6-Gbit/s SATA Spread-Spectrum Clock Generator Using Two-Stage Delta-sigma Modulator, Hong-Yi Huang, Li-Wei Huang, Wei-Sheng Tseng and Chih-Yuan Hsu, National Taipei University, Taiwan

FB2.2  A Spread Spectrum Clock Generator Using Digital Modulation Scheme, Chorng-Sii Hwang1, Huan-Chun Li2 and Hen-Wai Tsao2, 1National Yunlin University of Science and Technology, and 2National Taiwan University, Taiwan

FB2.3  All Digital Time-To-Digital Converter Using Single Delay-Locked Loop, Hong-Yi Huang, Yi-Jui Tsai, Kung-Liang Ho and Chan-Yu Lin, National Taipei University, Taiwan

FB2.4  A New Low Voltage, High PSRR, CMOS Bandgap Voltage Reference, Seiede Fateme Ashrafi1, Mohammad Chahardori2, and Seied Mojtaba Atarodi2, 1Niro Research Institute, and 2Sharif University of Technology, Iran

12:10 p.m. - 1:30 p.m. LUNCH (on your own)

Friday, September 19 - Afternoon

1:30 p.m. – 3:10 p.m.

 FA3:  CAD
Chair: Kaijian Shi, Synopsys
Co-Chair: Emrah Acar, IBM

FA3.1     A Timing Methodology Considering Within-Die Clock Skew Variations, Savithri Sundareswaran1, Sergey Gavrilov2, Roman Soloviev2, Rajendran Panda1, Lucie Nechanicka1 and Jacob Abraham3, 1Freescale Inc., 2IPPM, Russia, and 3University of Texas at Austin

FA3.2     X-Clock Routing Based on Pattern Matching, Chia-Chun Tsai1, Chung-Chieh Kuo2, Jan-Ou Wu3, Trong-Yen Lee2 and Rong-Shue Hsiao2, 1Nanhua University, 2National Taipei University, and 3De Lin Institute of Technology, Taiwan

FA3.3     An Automated Design Method for Chip Power Distribution, Di Phan, Chris Berry, Frank Malgioglio and Alan Wagstaff, IBM Corp.

FB3:  Communication and Processing

Chair: Mark Schrader, Harris
Co-chair: Gerd Ascheid, Aachen Univ. of Techn., Germany

FB3.1   A Low Power 1-Gbps Reconfigurable LDPC Decoder Design for Multiple 4G Wireless Standards, Yang Sun and Joseph Cavallaro, Rice University

FB3.2   High Performance IP Lookup Circuit Using DDR SDRAM, Xin Yang1, Jun Mu1, Sakir Sezer1, John McCanny1 and Earl Swartzlander2, 1Queen's University Belfast, UK, and 2Univ. of Texas at Austin

FB3.3   Power/Throughput/Area Efficient PIM-based Reconfigurable Array for Parallel Processing, Martin Margala1, Sohan Purohit1, Sai Chalamalasetti1 and Pasquale Corsonello2, 1University of Massachusetts Lowell, 2University of Calabria, Italy

FB3.4   A Discrepancy Computationless RiBM Algorithm and Its Architecture for BCH Decoders, Sangho Yoon and Hanho Lee, Inha University, Korea

3:10 p.m. - 3:30 p.m.  COFFEE BREAK

3:30pm – 5:30 p.m.
Chair: Kaijian Shi, Synopsys


Tutorial Track A

Tutorial Track B

3:30 p.m. -
5:30 p.m.

Design and Verification of Complex SoC with Configurable, Extensible Processors
Steve Leibson and Grant Martin, Tensilica, Inc.

A New Generation of C-Base Synthesis Tool and Domain-Specific Computing
Zhiru Zhang,
AutoESL Design Technologies, Inc